1. Technical Field
The embodiments herein generally relate to computer systems, and, more particularly, to cache management in computer systems.
2. Description of the Related Art
Moore's law indicates that computer processing speed grows at an astounding 60% yearly rate. In contrast, disks which are electro-mechanical devices have improved their access times at a comparatively meager annual rate of approximately 8%. Moreover, disk capacity grows approximately 100 times per decade, implying fewer available spindles for the same amount of storage. These trends generally dictate that a processor must wait for increasingly larger number of cycles for a disk read/write process to complete. A significant amount of performance research has focused on hiding this input/output (I/O) latency for disk bound applications.
Caching is a fundamental technique in hiding I/O latency and is widely used in storage controllers, file systems, and operating systems. The Storage Networking Industry Association (SNIA) defines a cache as “a high speed memory or storage device used to reduce the effective time required to read data from or write data to a lower speed memory or device.” Hereinafter, cache techniques will be discussed in the context of a storage controller wherein fast, but relatively expensive, random access memory is used as a cache for slow, but relatively inexpensive, disks. A modern storage controller's cache typically contains volatile memory used as a read cache and a non-volatile memory used as a write cache.
Read cache management is a well studied discipline. There are a large number of cache replacement techniques in this context, see, for example, LRU, CLOCK, FBR, LRU-2, 2Q, LRFU, LIRS, MQ, ARC, and CAR. In contrast, write caching is a relatively less developed subject. More particularly, there remains a need for a new technique for write cache management in the context of a storage controller equipped with fast, non-volatile storage (NVS).